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How persistent memory will change computing
Never Say Die
The same data storage hierarchy paradigm has been used for many years, and seemingly it works quite well. However, a new kind of data storage is coming that will completely disrupt this hierarchy and force the developer, user, and admin, to rethink how and where they store data. The general term for this storage is NVRAM (Non-Volatile Random Access Memory). In this article, I focus on something reasonably new – and most probably disruptive – called persistent memory (PM).
Looking back at the history of processors, one can see that layers of caching were added to improve performance. The first line of data storage are the CPU registers, which have the fastest and lowest latency of any storage in the system. However, the amount of storage is very small because of cost (as part of the CPU), and data had to be retrieved either directly from main memory (DRAM) or from disk storage, resulting in slow data access, and therefore slow performance.
To improve performance, caching was added to processors. Between the registers and main memory, Level 1 (L1), Level 2 (L2), and even L3 and L4 caches have been added. Typically the L1 cache is part of the processor (each core) and can store more data than the registers, but it is slower and has higher latency than registers.
The L2 cache is a bit larger than the L1 cache, but it is also a bit slower and has higher latency. Sometimes it is shared across two cores or more. The L3 cache another level above L2 is slower yet and has higher latency than the L2 cache. Typically the L3 cache works for all cores on the processor.
After the processor cache sits DRAM, or main memory. This can be fairly large, but again it has lower performance and higher latency than the caches. I hope you are noticing a trend.
All the registers, caches, and memory are volatile. If power is lost, the data stored in them is lost. On the other hand, storage that can survive a loss of power is typically disk or flash. The
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